Analog DevicesAD9548/PCBZ

AD9548/PCBZ is AD9548 Quad/Octal Input Network Clock Generator/Synchronizer Evaluation Board. The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH).The AD9548 generates an output clock synchronized to one of up to four differential or eightsingle-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references.The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

AD9548: Quad/Octal Input Network Clock Generator/Synchronizer Data Sheet (Rev E, 12/2013)

AN-1079: Determining the Maximum Tolerable Frequency Drift Rate of the AD9548 System Clock in Low Loop Bandwidth Applications

AN-1061: Behavior of the AD9548 Phase and Frequency Lock Detectors in the Presence of Random Jitter

AN-1064: Understanding the Input Reference Monitors of the AD9548

AN-1002: The AD9548 as a GPS Disciplined Stratum 2 Clock

AD9547/48: Profile Designer SW 

AD9547/48: Evaluation Board SW Overview 

AD9547/48: Evaluation Board Setup