Analog DevicesAD9559/PCBZ

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates two completely independent output clocks that are synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.

• Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
• LDOs are easily bypassed for power measurements
• 4 ac-coupled differential output SMA connectors (which can be reconfigured for up to 8 single-ended outputs.
• 4 inputs SMA connectors that accept either single-ended or differential signals
• USB connection to PC
• Microsoft Windows-based evaluation software with simple graphical user interface and support for both 64-bit and 32-bit operating systems.
• Easy access to digital I/O and diagnostic signals via I/O header
• Status LEDs for diagnostic signals

Schematic File  (pdf, 292 kB)

Bill of Materials  (xlsx, 26 kB)

AD9559 Evaluation Software  (zip, 52603 kB)

Web Install  (zip, 4195 kB)