Silicon Motion TechnologySM681GXB AES | PCIe 32GB 3D BGA SSD DRAM-Less C-tempSolid State-Laufwerke

The PCIe NVMe FerriSSD® family consists of SM689 supporting PCIe Gen3 x4 NVMe 1.3 and SM681 supporting PCIe Gen3 x2 NVMe 1.3 designed optimally for high-performance mission critical applications. By combining industry proven controller technology, NAND flash and passive components into a small single BGA package, PCIe NVMe FerriSSD® simplifies design efforts, reduces time-to-market while protecting from NAND technology migration concerns.

The SM689 supports embedded DRAM with Data Redundancy with PCIe Gen3 x4 interface - exhibiting sequential read speed of up to 1.45GB/s and sequential write speed of up to 650MB/s. The SM681 DRAM-Less series feature the best balance of saving/performance - cost saving from eliminating DRAM while maintaining DRAM-like performance via HMB (Host Memory Buffer). Both available in 3D TLC/MLC/SLC modes, the unique flexible design can support multiple capacity configurations ranging from 5GB to 480GB and include enterprise-grade advanced data integrity and reliability capabilities using Silicon Motion's proprietary end-to-end data protection, ECC and data caching technologies. Key Features End to End Data Path Protection SMI’s PCIe NVMe FerriSSDs incorporate full data error detection with recovery engines to provide enhanced data integrity throughout the entire Host-to-NAND-to-Host data path. The PCIe NVMe FerriSSD® data recovery algorithm can effectively detect any error in the SSD data path, including hardware (i.e. ASIC) errors, firmware errors and memory errors arising in SRAM, DRAM or NAND.

Key Features

End to End Data Path Protection

SMI’s PCIe NVMe FerriSSDs incorporate full data error detection with recovery engines to provide enhanced data integrity throughout the entire Host-to-NAND-to-Host data path. The PCIe NVMe FerriSSD® data recovery algorithm can effectively detect any error in the SSD data path, including hardware (i.e. ASIC) errors, firmware errors and memory errors arising in SRAM, DRAM or NAND.

NANDXtend™ ECC Engine

Conventional SSDs employ standard BCH and RS ECC (error correction coding) engines for initiate first-level correction using NAND shift-read-retries. In addition to this first-level error correction, PCIe NVMe FerriSSDs also implement a highly efficient second-level correction scheme using an LDPC (low-density parity check) code and a Group page RAID algorithm (a highly efficient redundant backup) to reduce potential dPPM at customer site while extending the service life of SSD.

IntelligentScan and DataRefresh to Enhance Data Integrity

SMI’s proprietary IntelligentScan function will activate automatically to scan recharge, repair or retire the cell block (DataRefresh) according to the host behavior and working environment (eg. ambient temperature). As a result of the combination of IntelligentScan and DataRefresh, PCIe NVMe FerriSSD® can effective prolong its service life much beyond typical NAND specifications.

Read this White Paper on Silicon Motion’s PCIe FerriSSD

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