Memory access is so common in MCUs, DSPs and SoCs that it typically accounts for a significant percentage of a processor’s power consumption.
Consequently, the never-ending quest to reduce processor power consumption often focuses on the chip’s memory architecture. Similarly, memory architectures are scrutinized, tinkered with and tuned as a means of achieving better processor performance.
Von Neumann vs Harvard Architecture
An early example of trying to simultaneously reduce power consumption and increase performance was the Harvard memory architecture, which allocated separate memory spaces for program instructions (code) and data. Separate memory spaces imply separate memory buses, which meant that the program code and data could be accessed simultaneously.
This was a significant departure from the von Neumann memory architecture, which stored both program and data in the same memory space.
The Harvard design strategy was simplicity in itself: Reducing the number of clock cycles required to complete the same computational task would boost performance and reduce power consumption. Over the decades that followed, the tradeoffs of chip design became far less simple.
PIC Microcontroller Architecture
As processor design evolved, memory architectures morphed into hybrids that use numerous techniques—such as cache memory—to handle the interplay between program bits and data bits. But in the interests of understanding how these hybrids evolved, it is worth reviewing a few aspects of the pure Harvard architecture.
First, the advantages of different memory types can be exploited. Program memory that is stored in on-chip ROM, for example, makes it virtually impossible to tamper with the code. On the other hand, if the application designer wants to be able to upgrade or reprogram the code once the chip is in the field, flash memory would be a better choice.
The type of system in which the processor will be used can still favor the pure Harvard architecture. When the cost and power savings derived from omitting caches is critically important, for example, we sometimes—but not always—encounter pure Harvard memory configurations.
PIC Microcontroller Applications
Two examples are DSPs and MCUs in certain applications. When DSPs are used to execute small, highly optimized audio- or video-processing algorithms, the chip design strategy calls for avoiding memory caches because the DSP’s behavior must be extremely reproducible. Consequently, some DSPs have multiple data memories in distinct address spaces to facilitate SIMD and VLIW processing.
In many of the simpler embedded applications, MCUs store a few lines of program code in flash memory and a few kilobytes of data in SRAM. In this design scenario, the system designer can take advantage of the Harvard architecture’s primary advantage: to speed processing by concurrent instruction and data access.
Bifurcated memory offers another advantage: Program and data memories can have different bit widths. For example, 16-bit-wide instructions and 8-bit-wide data. Some of Microchip Technology’s PIC and AVR families of MCUs employ this design strategy. Even in these cases, there are circumstances in which chip designers empower system designers with the ability to employ special instructions that access program memory as though it were data. And that is one of many reasons why modified Harvard architecture processors evolved.
PIC Microcontroller Advantages and Disadvantages
In many embedded applications, very small memory spaces are all that are needed. One of the advantages that 8-bit MCUs offer is that they can run code with using very little program memory or data memory. Microchip’s 8-bit PIC and AVR8 product lines, for example, have maximums of 28 KB of program memory (flash) and 2 KB of RAM. The chips, therefore, can have a tiny physical footprint, use little energy and be purchased at a very low cost. But sometimes, this “running lean” advantage has drawbacks.
Accessing a table of constant values is an inherent component of executing an application’s algorithms. Because these constants are part of the manipulation of data, in a pure Harvard architecture, they should be stored in data memory. But when you have only 2 KB of RAM to work with, that can be a waste of scarce RAM resources.
The obvious solution, of course, is to store data constants in program memory. But under normal “Harvard” circumstances, the CPU cannot read these constants directly. The workaround technique is aptly called an access-instruction-memory-as-data modified Harvard architecture. The difference is the addition of a special set of instructions that allow reading constants from code memory into the CPU’s registers.
It should be noted that the term “modified Harvard architecture” does not have a widely agreed upon definition. This has generated a good deal of confusion. One possible definition of a modified Harvard architecture is that it has shared memory but separate program and data buses. This is simple enough, but it includes so many actual processor designs that it doesn’t tell us much. Our time is better spent looking at a couple of modified Harvard schemes that are in common use and the practical issues of the system designers that use them.
What is a Memory Hierarchy?
The split-cache architecture is an outstanding example. It creates memory hierarchy with CPU caches that separate instructions and data.
One advantage of using a memory hierarchy is that it doesn’t impose the programming complications and limitations of the pure Harvard architecture. Another is that split-cache improves performance. Still another advantage is that it allows program memory space and data memory space to be expanded using a single external memory device to accommodate both program instructions and data (and without using special-purpose instructions). So it’s a good idea.
From an application programmer’s perspective, however, split-cache looks a lot like the von-Neumann architecture because code is written as though it were von Neumann. Split-cache is, in fact, sometimes referred to as an “almost-von-Neumann” architecture.
So while it can be useful to discuss modern processor architectures in terms of historical predecessors as a way to understand architectural evolution, trying to settle on a strict definition of modified Harvard architecture does not lead us anywhere.
Conclusion
The Harvard architecture—and its name—began in the computer world. During World War II, Harvard University engineers developed an electromechanical computer called the Mark 1. It read its instructions from punched paper tape. Another tape contained data. This separation of data and instructions became known as the Harvard architecture.
Chip designers left the paper tape and mechanical relays behind but adapted the architecture to early microcontrollers such as the 8051—as well as some microprocessors. On a parallel path, chips were being designed with the von Neumann memory architecture and its unified memory space.
Chip design never stands still. Designers are often confronted with scenarios in which the choice between Harvard and von Neumann is far from clear-cut. Mixing and matching comes naturally to engineers. They do whatever it takes to meet performance, power consumption and cost targets. Sometimes these solutions are called “enhanced” or modified Harvard architectures if for no other reason than that people are in the habit of asking, “What memory architecture does this processor use?”
The Harvard architecture’s story is the story of electronic design. It is not unique, but it is as good an example as any of progress through innovation.