1200V CoolSiC™ MOSFET High Performance including High Reliability

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Introduction 

SiC MOSFETs with blocking voltages of 1200V are interesting in application fields such as solar converters, UPS, battery chargers as well as industrial drives. These applications benefit from the reduction of switching- and conduction losses; the thermal budget can be shifted to achieve higher switching frequencies to reduce the physical size of passive components and minimize the cooling effort, weight and cost.  

The CoolSiC™ Trench MOSFET design was developed to limit the electric field in the gate oxide in on-state as well as in off-state. An attractive specific on-resistance for the 1200 V class is provided, achievable even in mass production in a stable and reproducible way. The low on-resistance is already achieved at diving voltage levels of V_GS= 15V.

The gate-source-threshold voltage is benchmark with 4V. These boundary conditions are the baseline for transferring quality assurance methodologies established in the silicon power semiconductor world in order to guarantee FIT rates expected in industrial and even automotive applications.

Figure. 1: CoolSiC™ MOSFET lead product overview

For fast switching IGBTs and SiC transistors, the design of the package is equally important.

With a look to the available power module platforms, some packages are extremely advantageous towards fast switching SiC devices. The stray inductances need to be as low as possible, but in addition a highly symmetric design is needed as well.

The Easy-Module platform for example is predestined for this use. . In contrast to well-known standard packages with baseplate, the Easy-Module platform allows building a highly symmetric, low inductive design. For this reason the popular and flexible Easy1B power module is used to implement a first SiC half bridge and booster solutions optimized for photovoltaic, electric vehicle charging and uninterruptable power supplies.

The flexible pin grid of Easy modules simplifies PCB layout and offers a stray inductance below 10 nH. This is a huge improvement step down by 70-80% compared to existing solutions like EconoDUAL™, or standard SIXPACK designs. This represents a valuable step in power module design.

Figure 1 depicts an overview about the lead products. The listed products are just the first step getting the broad optimized portfolio of CoolSiC™ MOSFET products with further devices currently under development.

Device design philosophy

Switching losses of SiC-MOSFETs are usually quite low and especially almost temperature independent. Advanced design activities focus on the area specific on-resistance as the major benchmark parameter for a given technology. For 4H-SiC based planar MOSFETs an extraordinary high interface trap density close to the conduction band has to be dealt with. This ends up at very low channel motilities and therefore high contributions of the channel to the total on-resistance. The high defect density is reflected in various peculiarities of SiC-MOSFET based devices. An observed way to overcome this dilemma is to increase the electric field applied across the oxide in on-state, exceeding values usually being used in silicon based MOSFET-devices. Such high fields in the oxide in the on-state can potentially accelerate the wear out. This can be seen as a long term reliability risk, in particular with respect to the high defect density of SiC-substrates.

Based on those considerations, it is obvious that planar MOSFET-devices in SiC have actually two sensitive areas with respect to oxide field stress, as sketched in the left part of figure 2

Figure. 2: Left part: Typical structure of a planar MOSFET revealing two sensitive areas with respect to oxide field stress. Right part: Typical structure of a Trench-MOSFET, critical issue is the oxide field stress at the trench’s corners.

First, the usually discussed stress in reverse mode in the area of highest electric field close to the interface between drift region and gate oxide and second the overlap between gate and source which is stressed in on-state.

A high electric field in on-state is seen as more dangerous since no device design measures are in place which could reduce the field stress during on-state. Thus, the overall goal is to combine the low R_DSon potentially offered by SiC with an operation mode where the part remains in the well investigated safe oxide field-strength conditions. In the on-state, this can be achieved today by moving away from the planar surface with its high defect density towards other, more favorable surface orientations.

Gate Oxide Reliability

The challenge regarding the gate oxide reliability of SiC MOS devices is to ensure a low enough failure rate, including extrinsic defects, throughout a desired life time under given operation conditions. The typical industrial requirement targets of << 100 ppm in 20 years of operation. The root cause for extrinsic defects in the gate oxide of SiC MOS devices is mainly ruled by defects within the substrate material, epitaxial process and, to a less significant contribution, by the remaining process chain. Tests of commercial MOSFET products reveal that this issue is still a serious concern for the use in industrial systems.

Therefore, long time tests with a larger number of devices were performed to investigate extrinsic gate oxide failure rates for Infineon’s CoolSiC™ MOSFET. An experiment was done in two groups of 1000 discrete devices each, performed at 150°C under constant gate bias stress for three sequences of100 days. Fig. 9 summarizes the test results. After 100 days, the gate source voltage was increased by +5V.

These statistics fit well to the linear E-Model. An acceleration factor was determined for best fit corresponding to the solid lines in figure 3.

By extrapolating this result to an operation life time of the device of 20 years using the recommended voltage levels, the model predicts a failure rate of 0.2 ppm. Hence, there is evidence to have a reliability of the gate oxide similar to the one known from IGBTs, which fits perfectly to the typical industrial requirement.

Figure. 3: Long term test: the number of fails is plotted over stress days. In total 2 groups of 1000 devices where tested at 150°C with constant gate voltage V_GS which is indicated. V_GS is increased by 5 V every 100 days. Each dot represents a fail. Solid lines represent the prediction by linear E model

Dynamic Performance

Being a unipolar device, the dynamic performance of the SiC-MOSFET is mainly ruled by its capacitances. The device was designed to have a small Gate-Drain reverse capacity C_rss compared to the input capacity C_iss. This is beneficial  to prevent the MOSFET from parasitic turn-on and sophisticated gate driver circuitry when operated in a half bridge configuration.

Figure 4 displays the typical switching losses of a half bridge with single devices mounted in a 4-pin TO-247 housing as function of drain current. The turn-off energy E_off is nearly independent on the load current since it is dominated by capacities, whereas the turn-on energy E_on increases linearly with current.

At an application current of 20A, the total losses E_tot sum up to 0.43 mJ which enables switching frequencies in the regime of 50-150 kHz.

Figure. 4:   Typical switching energies  as a function of drain current I_D.
Conditions: V_GS = 15 / -5 V, R_Gext = 4.5 Ω, V_DS = 800 V, T_vj =175° C, 4 leg TO-247 in half bridge configuration

The 4^th pin of the TO-247 package is to connect the gate driver to the source i, avoiding the negative feedback due to source stray inductances. Thus, in comparison to a 3-leg TO247 half bridge configuration, about 100 mJ total switching energy can be saved at a current of 20 A. This is a reduction of about 30% based only on the optimization of the package using the same die.

Figure 5 provides an insight to the MOSFET’s ability to easily control the voltage slope dv/dt by adapting the gate resistor R_G. This is particularly of interest for drive applications. However, the reduced voltage slope dv/dt is paid for by increased switching losses.

Figure. 5:   Typical switching losses (left axis, black curves) and maximum dv/dt values (right axis, red curves) vs. R_Gext.
Conditions.: V_DS=800 V, I_D = 40A, V_GS = 15 / -5 V, T_vj=175°C, 3 leg TO-247 in half bridge configuration

Obviously, the loss reduction will be more prominent in applications where there is no dv/dt limitation and grows with the switching frequency. This is common in DC-DC boost or buck/boost topologies, providing the benefit of smaller, lighter and lower cost magnetic components. Various studies have already proven that – even with more expensive power switches – the cost of material can be reduced for a wide spectrum of applications. This number of applications will increase over the mid-term time frame based on the anticipated cost reduction over time for SiC based components.

Static Performance

Key characteristics of the static output characteristic of a MOSFET is the channel resistance R_DS(ON).The newly introduced die features a typical on-resistance of 45 mΩ at room temperature at V_GS = 15V. A positive temperature coefficient of the on-resistance makes the devices predestined to be used for paralleling. In Figure 6 the output characteristic  is given in direct comparison to the state of the art 1200V high speed 3 IGBT. Due to the threshold-free on state characteristic the conduction losses especially in partial load can be reduced enormously. On system level, the feature of threshold-free conduction behavior offers a significant potential for loss reduction. Many systems are operated under partial load conditions for a large portion of their lives and conduction losses are considerably lower compared to the competing standard IGBT technologies. Even at very low switching frequencies of less than 5 kHz and unchanged dv/dt slopes it can be seen that a threshold-free switch with integrated body diode, in synchronous rectification mode, offers a potential of 50% total loss reduction compared to a commercial IGBT solution available today.

 

Figure. 6: Typical SiC-MOSFET output characteristic in comparison to IGBT solutions

In contrast to booster-stages, typical inverter application equire a well-defined short circuit capability especially in case of failure events in the field. Reflecting this important need, the CoolSiC™ MOSFET is the first SiC-MOSFET on the market with a specification of short circuit robustness.

In contrast to typical DMOS behavior the transfer characteristics (25°C /175°C) reveal a crossing point already at V_GS = 12V. Above 12V, the current decreases with temperature which is beneficial to limit the saturation current in a short circuit event.

Figure 7 denotes the most critical, so called hard short circuit event. The behavior and robustness under short circuit was analyzed in detail to allow a specification of short circuit time to achieve 3µs.

Figure. 7: Typical short circuit behavior of CoolSiC™ MOSFET in TO-247-4 at room temperature

Figure 8 denotes the most critical, so called hard short circuit event. The behavior and robustness under short circuit was analyzed in detail to allow a specification of short circuit time to achieve 3µs.

In contrast to standard IGBTs the short circuit current rises to factor of 10 compared to the nominal current of the device.  After the first peak the saturation current decline to a much lower level due to the temperature depending characteristics described above.

Summary

Infineon is a pioneer in the commercial use of the SiC technology. As the first company worldwide, SiC based diodes were introduced in the market as early as 2001. Meanwhile the 5th generation of such parts is available as discrete devices. The product design was always carefully oriented on a beneficial cost-performance evaluation.

The concept of Infineon’s SiC-Trench-MOSFET combines a low on-resistance with an optimized design preventing too high gate oxide field stress, providing IGBT like gate oxide reliability. The SiC-Trench-MOSFET features superior performance in terms of switching behavior and losses. The analysis done confirms a full controllability of the voltage slopes in booth, turn-on and turn-off transients. The current slopes for turn-on as well can be controlled by the gate resistor. In turn-off, the di/dt is determined by parasitic capacitive effects.

Furthermore the device is the best available mix of electrical performance and robustness features like the short circuit reliability.

With the CoolSiC™ MOSFET technology, the beginning of a new era of power electronics in terms of power conversion efficiency and power density has begun.

Acknowledgment

I would like to thank all Infineon colleagues for their contribution which made this CoolSiC™ MOSFET technology possible, in particular the members of the concept-, technology- and module- development team at the Infineon sites: Erlangen, Villach and Warstein.

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