The demand for increased bandwidth to support things like video streaming and cloud computing is driving the development of faster networking equipment. In order to make the best use of existing network infrastructure, new designs combine high-speed data transmission with greater port density and functional integration with OTN switching. In this article, learn how DSPLL® clocks from Skyworks deliver any-frequency, any-output clock synthesis to modern telecommunications equipment designs.
Simplified Clock Generation in OTN and 10/40/100G Ethernet
Skyworks has developed a new portfolio of clock generators and jitter attenuators optimized for high-speed, frequency-flexible, ultra-low-jitter clock synthesis. These clock devices enable system designers to design “any-port, any-protocol” line cards with industry-leading jitter performance of < 100 fs RMS typical (12 kHz to 20 MHz). The devices also support “on-the-fly” frequency reconfiguration. This feature dramatically simplifies system design, enabling significantly lower cost and more flexible service provisioning in SDN environments. Service provisioning allows network operators to respond to users’ rapidly-changing demands for diverse voice, video, and data services, such as cloud storage, video streaming, and mobile services.
Fourth-Generation DSPLL vs. Traditional High-Performance Clock Architectures
The Skyworks Si5345/44/42 jitter attenuators leverage a unique, proprietary architecture that delivers greater frequency flexibility, lower jitter, lower phase noise, and improved spurious performance compared to traditional clock architectures. These new devices have been designed using the most advanced process technology for any standalone clock device (55 nm CMOS), making it possible to deliver unparalleled performance and frequency synthesis flexibility in a single, unified architecture.
Fourth-Generation DSPLL Enables High Port Density Line Cards
Next-generation 10/40/100G OTN switching and transmission equipment is transitioning to higher port densities to further scale network capacity. This is increasing the market need for more highly integrated physical-layer timing devices that provide multiple independent PLLs in a single IC, minimizing the PCB footprint in tightly packed, high-density line cards. The fourth-generation DSPLL architecture is compact and scalable, making it possible to build monolithic, single-chip multi-PLL jitter attenuating clocks that are significantly smaller and lower jitter than competing solutions.
Conclusion
Skyworks’ fourth-generation DSPLL clocks leverage cutting-edge, mixed-signal analog design and 55 nm CMOS technology to deliver any-frequency, any-output clock synthesis with industry-leading PLL integration and jitter performance. Hardware designers can leverage these new products to minimize the timing component BOM count and complexity required to build any-protocol, any-port, high-density 10/40/100G OTN and Ethernet line cards.