Architects and designers of modern electronics systems face a dizzying array of challenges. Today’s systems require more features, higher performance, increased bandwidth, lower power, smaller form factors, reduced cost and faster development times than yesterday’s. You can bet that future systems will face even more challenges. Perhaps the most difficult aspect of meeting these conflicting requirements involves making the right trade-offs between different implementations.
Correctly balancing board space, development time, cost, reliability and flexibility for the power management subsystem can be one of the most challenging decisions due to the wide range of options available to the designer. Each option comes with its own set of advantages and disadvantages which need to be carefully weighed against the overall system requirements and constraints. For example, Figure 1 below shows a discrete implementation of a typical power management system. The input voltage, VIN, provides the power source and the output, VOUT, connects to the boards’ specific power rail. The Pulse Width Modulation (PWM) controller periodically enables the gate drive for the power MOSFETs that deliver the power to the output. The power inductor and the compensation network create the feedback loop used by the PWM controller to deliver the power required by the system dynamically.
Figure 1: Typical Controller, Regulator and PowerSoC Solution (Figure courtesy of Altera, now part of Intel)
Levels of Integration
The solutions illustrated in Figure 1 above show the common Controller-based implementation, which requires the most external components, the Regulator-based implementation, which integrates the power MOSFETs. Enpirion® PowerSoC solutions from Altera integrate the controller, the gate driver, power MOSFETs, inductor and some of the compensation network. Board space is significantly reduces this more integrated solution. (We will see later that this advanced level of integration provides many additional advantages to, but let’s focus on board space for now since that is the most obvious advantage).
Board space savings can be multiplied on most board designs since a board often requires multiple power rails for processors, memories, FPGAs and DSPs. For example, a device’s core voltage can depend on the type of process being used, I/O voltages can change based on the interface required, and analog circuitry can require a different voltage level all together. Thus, if multiple power rails are needed, the board space savings for a single point of load power management subsystem will accrue for each subsystem and can result in very significant savings.
Input Voltage Selection
Modern board designs usually select between a 12V source or a 5V source as the main power input to the power rail, or often called the point of load, power management system as converters with an increased input voltage range have become available. Using a 12V converter eliminates the 12V to 5V conversion step, often required by 5V implementations, when the chassis power that the board plugs into is at 12V. The 12V solution can thus reduce the bill of materials and improve operating efficiency.
Often 5V solutions can have other advantages that out-weigh those provided by a 12V implementation. A detailed comparison covering the key elements that contribute to an implementation footprint is often required to scope out the most efficient solution for your design. For example, a 5V solution usually has a higher operating frequency which results in smaller capacitor and inductor sizes. Integrated 5V solutions can also have even smaller solution sizes. Often external component count in the compensation network is less for a 5V solution, which further reduces board space.
In 5V solutions, only one 12V converter is required per board, the added board space is amortized over each rail. For systems with multiple rails this added board space can end up being negligible. The board space being saved in 5V point of load implementations is often close to the high-power high-pin count computing elements. This space is often considered very valuable in comparison to other parts of the board since it tends to be much more constrained in terms of device placement, signal routing and susceptibility to noise. Having a smaller point of load thus simplifies board design and allows additional trade-offs to achieve an optimal mix of board space, performance, and schedule.
Efficiency gains from eliminating a 12V to 5V converter can often be overcome by the higher efficiency the 5V solution provides at the point of load. As a simple comparison, if the 12V to 5V converter operates at 92% efficiency and the 5V to 3.3V converter operates at 95% the overall system efficiency is 87.4% at full load. Compared to a 12V to 3.3V converter operating at 88-89% at full load the 5V solution is operating at virtually the same efficiency as the 12V solution. Also note that the increased efficiency of the 5V point of load solution reduces heat generate near the compute elements. This can further mitigate any overall efficiency benefit the 12V solution might be thought to have.
Figure 2: Efficiency Comparison with and without 12V to 5V Converter (Figure courtesy of Altera, now part of Intel)
Other important advantages are available with 5V point of load solutions. Due to their smaller footprint, higher switch frequency and lower inductance, output voltage ripple and accuracy are improved over more discrete solutions. High levels of integration also offer better electromagnetic interference (EMI) performance when compared to discrete solutions. Radiated EMI comes from high rates of change in currents flowing in loops (high di/dt). Because the radiated power is proportional to the radius of the current loop and decreases by R8, a smaller radius, like that offered by more integrated solutions, can dramatically decrease EMI effects.
Not to be overlooked is the advantage an integrated solution provides during the development cycle. An integrated solution using an Enpirion PowerSoC requires less design hours than a discrete solution- as much as 45% less for a typical design. The number of steps required during a typical development cycle can be almost 3 times as many for a discrete solution. Steps like selecting components, tuning the compensation network, and performing time domain analysis and simulation, just to name a few, are not required when using an integrated solution. In addition, the opportunities for errors and bugs are much reduced when using an integrated solution. This dramatically reduces risk to both the development schedule and development cost. The opportunity cost of spending valuable engineering time on power supply design, instead of the key features that will clearly differentiate a design from competitors should also be considered.
Let’s now look at a specific implementation to better understand how some of these key trade-offs can be evaluated.
Altera EN6362QI High Integration and Small Footprint
By integrating many of the typically external supporting components while achieving high efficiency, the EN6362QI 6A DC-DC step-down converter from Altera’s Enpirion series provides outstanding power density. The EN6362QI is designed, characterized, and qualified as a complete power system that includes the inductor, power switches, gate drive, controller, and compensation all in a small 8 x 8 mm QFN package. This provides the designer with a low risk solution with industry best FIT rates that are 4 times better than those that result from typical discrete solutions.
The EN6362QI is designed to meet the precise voltage and fast transient requirements of high performance FPGAs, ASICs, DSPs, and processors while using a total solution size of only 170 mm2. A typical implementation is illustrated in the below figure and shows the small number of external components required. Discrete solutions typically require up to 7 times more area, area that can be used to add high value features or can be eliminated to reduce board cost and form factor size.
Figure 3: Altera’s EN6362QI 6A PowerSoC DC-DC Step-Down Converter (Figure courtesy of Altera, now part of Intel)
The EN6362QI can deliver 6A continuous operating current across the full industrial operating temperature range without thermal de-rating. Figure 3 below shows the conversion efficiency of the EN6362QI over the 6A output current range, which operates at a peak efficiency of 96% that is nearly flat over the full output current range, making it an excellent solution for systems that have varying output current needs. This is an increasingly common requirement for systems where power is ‘modulated’ based on the natural variations in computing and bandwidth needs of the overall system.
Figure 4: Altera’s EN6362QI Efficiency at VIN = 5V and VOUT = 3.3V (Figure courtesy of Altera, now part of Intel)
In addition, faster response to load transients is a critical requirement to reduce the chance of system instability due to power ‘starvation’ or even damage caused by sustained high voltage on sensitive components. This is particularly important in systems with dramatically changing load requirements like those found in FPGA, DSP and high-performance processor based systems. The EN6362 has a 60 μs response time, due to the combination of lower inductance and higher regulator bandwidth than a typical discrete solution.
Conclusion
Altera’s EN6362QI PowerSoC solution offers significant benefits over discrete power solutions. These benefits include reduced PCB cost due to the PowerSoC’s smaller solution footprint, better EMI performance because of their more compact implementation, and improved system reliability. Altera’s Enpirion PowerSoC solutions also deliver faster, easier, lower cost and lower risk development that improves overall time to market. Visit the resources listed below to watch the overview video, download the data sheet or to order an evaluation board.
Altera EN6362 PowerSoC Product Page and Ordering Information:
https://www.arrow.com/en/products/en6362qi/intel
Comparison Diagrams:
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EXAMPLE DIAGRAM FOR SHOWING EFFICIENCY COMPARISON: