The innovative Source-Down package flips the silicon die inside, allowing for the source to be connected to the thermal pad. This offers significant benefits over today's drain-down industry standard by enabling a larger silicon die, reducing RDS(on) and offering superior thermal performance.
Infineon's Source-Down package supports customer requirements for high power density and optimized system level efficiency. In addition, new layout options offer more flexibility for PCB designers to improve thermal and electrical performance at the system level. The product family is currently available in 25V and 40V options with additional voltages currently being worked on.
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Key Features
- • Major reduction in RDS(on)– up to 25 percent
- • Superior thermal performance in RthJC
- • Optimized layout possibilities
- • Standard and center-gate footprint
Key Benefits
- • High current capability
- • More efficient use of PCB area
- • Highest power density and performance
- • Optimized footprint for MOSFET parallelization with center-gate
General Applications
- • Drives
- • SMPS
- • Server
- • Telecom
- • OR-ing
- • Battery management / Battery protection
- • Power tools
- • Charger
Related Products
| OPN | Product Description | Part Class | Static Sensitive | RoHS Compliant | Lead Free |
| IQE013N04LM6ATMA1 | 40V OptiMOS™ MOSFET in Source-Down PQFN 3.3x3.3 standard gate | Low-voltage MOSFETs | T | Y | Y |
| IQE013N04LM6CGATMA1 | 40V OptiMOS™ MOSFET in Source-Down PQFN 3.3x3.3 center gate | Low-voltage MOSFETs | T | Y | Y |
| IQE006NE2LM5ATMA1 | 25V OptiMOS™ MOSFET in Source-Down PQFN 3.3x3.3 standard gate | Low-voltage MOSFETs | T | Y | Y |
| IQE006NE2LM5CGATMA1 | 25V OptiMOS™ MOSFET in Source-Down PQFN 3.3x3.3 center gate | Low-voltage MOSFETs | T | Y | Y |
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