When designing noise sensitive devices such as cellular and satellite communications equipment, test and measurement instruments, medical instrumentation, and low power wireless products, it is important to maintain a low noise environment to ensure that the device can operate as intended.
One of the largest sources of noise in modern systems is DC-DC switching power supplies. Although they are able to efficiently support high power loads, noise from switching supplies can often be seen from the primary switching frequency up through several hundred Megahertz. In devices that contain RF mixers, voltage controlled oscillators, analog front ends, and other noise-sensitive circuits, this noise can inhibit optimal operation, particularly when high efficiency power supplies are required.
Fortunately, low dropout linear regulators (LDOs) are available as a low noise alternative to switching supplies. Their balance of efficiency and low noise at moderate loads makes them ideal solutions for noise sensitive applications. LDOs are similar to traditional linear regulators, but their open collector or open drain schematic topology results in a regulator that is easily driven to saturation with a small difference between the input voltage and the regulated output voltage. Bipolar and FET options are available, but FET implementations generally have better efficiency and thermal characteristics, particularly when the supply voltage is just high enough to stay above the dropout voltage during all operating states. LDO circuits also take up substantially less space on PCBs because they do not require a large inductor and need fewer capacitors and other related discreet components; typical designs require only a handful of components around the LDO.
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Of particular importance to noise-sensitive systems, LDOs are inherently able to reject noise and ripple from upstream switching power supplies. This makes them ideal for situations when switching noise could interfere with circuits that are susceptible to power supply noise. This property is known as the Power Supply Rejection Ratio (PSRR), and it is calculated using the formula
PSRR=20 log (Vinput ripple / Voutput ripple)
Standard LDOs can exhibit good PSSR from 10 Hz through 1 MHz, and higher performance models are available that extend the noise rejection through 5 or 10 MHz. Rejections of 20 – 70+ dB are possible depending on the design of the LDO, although higher PSRR usually correlates to higher quiescent current and output noise. Quiescent current is the combined bias current and gate drive current of the series pass element, and represents the difference between the input and output currents. Quiescent current on bipolar transistors increases with load, while FETs exhibit a constant, low quiescent current. Output noise is the RMS value of the broadband noise at the output of the LDO given an input with no ripple. This is typically in the 10s of microvolts, but advanced methods exist to reduce this noise even further.
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One method to further reduce noise is to use a feedforward capacitor between the output pin and the feedback pin. The capacitor provides a lower impedance path for high frequency signals, which enhances the PSRR and dynamic response of the LDO while simultaneously lowering the output noise. The value of the capacitor must be chosen carefully, however, as larger feedforward capacitors can interfere with proper start-up and large transient load operation.
Despite their strengths in providing an efficient and low noise output, LDOs still have output current limitations and require methods to sink heat from the regulators. Fortunately, specialized methods have been developed to address these limitations and extend the benefits of LDOs into more applications. Several manufacturers have developed LDOs that can have their outputs tied together to provide responsive, high current power sources in situations where a single LDO would either be unable to supply sufficient output current or would exceed its maximum junction temperature under the expected loads. These solutions are well suited to FPGA designs that have low 1.3 or 1.8V internal logic, as well as server backplanes and other applications that require ultra-low noise and exhibit very high switched loads. Because low logic thresholds make power supply noise a critical factor in these systems, paralleled LDOs that provide a responsive power source with high rejection of switching noise become ideal choices.
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For the most sensitive instrumentation, test and measurement systems, and audio applications, even standard LDOs may not provide a quiet enough output voltage for a design to meet its performance goals. For these applications, ultra-low noise LDOs are available, although they are often less efficient and have reduced output current capacity compared to noisier alternatives.
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Devices that are sensitive to power supply noise require very quiet power sources. LDOs can provide an excellent option in these applications if they are well-matched to the systems they are designed into. With smart choices that optimize output power needs, efficiency and thermal requirements, and system noise sensitivity thresholds, LDOs can provide an ideal solution and help ensure proper circuit operation.