High Speed Board Design Guidelines Webinar
Date: Monday, May 10, 2021
Time:
- 9:00 am PST
- 12:00 pm EST
- 6:00 pm CET
When designing high-speed, high-power devices on a PCB, signal and power integrity concerns come to mind.
This webinar will review best practices to follow for PCB design, such as that of MoSys using SerDes as fast as 25 Gbps as the interface technology in its memory devices.
Attendees will learn about:
● Impedance control layout guidelines
● Coss-talk
● Layout of SerDes traces
● Power integrity
Can’t attend the live event? We’ve got you covered! Register now, and we’ll send you a link to view the webinar on-demand after the live broadcast.