RISC-V is an open instruction set architecture (ISA) founded by industry leading companies and research institutions. RISC-V is poised to become the standard open architecture for industry implementations under the governance of the RISC-V foundation. A RISC-V core implemented in an FPGA has distinct advantages over competing soft processor FPGA solutions, including portability, innovation, security and safety. Microsemi is the first FPGA provider to offer the RISC-V IP core and comprehensive software development tools for embedded designs.
Hi, I’m Laura, an applications engineer with Arrow.com here to talk with you today about the RISC-V IP processor core and what it can mean for your design. RISC-V is an open instruction set architecture (ISA) founded by industry leading companies and research institutions.
A RISC-V core implemented in an FPGA has distinct advantages over competing soft processor FPGA solutions, including portability, innovation, security and safety. Microsemi is the first FPGA provider to offer the RISC-V IP core and comprehensive software development tools for embedded designs.
By virtue of its free and open source platform, RISC-V cores give embedded designs a leg up on the competition. Its royalty free and can first be implemented in an FPGA and then targeted to an ASIC, license free. This portability translates into lower costs for developers. Collaboration from the global user base of the RISC-V community encourages innovation in a major way and Microsemi FPGAs are built to take advantage. The open source RTL design of the RISC-V core enables inspection of the core. This is ground breaking and allows a true trusted platform that goes hand in hand with the secure flash on the Microsemi FPGAs. Security applications can boot from the secure on board flash. And safety applications can also leverage RISC-V to instantiate multiple cores, or implement two different yet functionally equivalent cores to ensure fault tolerant operation.
The RISC-V RV32IM IP core offered by Microsemi offers leading edge features backed by an ecosystem designed for fast, secure development, which is why they’re a perfect fit for Microsemi’s IGLOO2, SmartFusion2, and RTG4 FPGAs. The Eclipse-based SoftConsole IDE Microsemi provides as part of its RISC-V launch is a complete Linux based toolchain that will allow an even broader engineering base to develop RISC-V applications with Microsemi FPGAs. It’s part of their larger Libero SoC design suite, which gives engineers a complete development ecosystem to maximize RISC-V capabilities—from entry to analysis to some of the best debug tools on the market—all designed to get your product to market faster.
The result is a versatile core that can meet specialized demands, but is also extremely stable and secure, which fits nicely into Microsemis FPGA portfolio, which offers up to 50% lower power devices with proven IP security and SEU immune FPGA fabric.
RISC-V is ideal for your next processor based design. Its capabilities are built on a fixed ISA, offering complete portability, trust and community development, all of which can be leveraged with a Microsemi FPGA. With the introduction of the RISC-V RV32IM IP core Microsemi FPGAs are opening the path for groundbreaking innovation. Never before has a processor allowed designers to inspect, modify, adapt, collaborate and migrate their design to the best platform for their product. Microsemi’s low power FPGAs with proven security and embedded flash are a natural fit for this new paradigm. The only thing missing is you.